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cy62148ev30 mobl ? 4-mbit (512 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05576 rev. *l revised july 6, 2011 features very high speed: 45 ns ? wide voltage range: 2.20 v to 3.60 v temperature range: ? industrial: ?40 c to +85 c ? automotive-a: ?40 c to +85 c pin compatible with cy62148dv30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 7 ? a (industrial) ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 36-ball very fine ball grid array (vfbga), 32-pin thin small outline package (tsop) ii, and 32-pin small outline integrated circuit (soic) [1] packages functional description the cy62148ev30 is a high performance cmos static ram organized as 512 k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption. placing the device into standby mode reduces power consumption by more th an 99 percent when deselected (ce high). the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. . note 1. soic package is available only in 55 ns speed bin. a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 13 a 14 a 15 a 16 a 17 row decoder column decoder 512k x 8 array input buffer a 10 a 11 a 12 a 18 logic block diagram i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 2 of 16 contents pin configuration .............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 data retention characteristics ........................................ 5 switching characteristics ................................................ 6 truth table ........................................................................ 8 ordering information ........................................................ 9 ordering code definitions ..... ...................................... 9 package diagrams .......................................................... 10 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc ? solutions ....................................................... 16
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 3 of 16 pin configuration [2, 3] product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 (a) f = 1 mhz f = f max min typ [4] max typ [4] max typ [4] max typ [4] max cy62148ev30ll vfbga industrial 2.2 3.0 3.6 45 2 2.5 15 20 1 7 tsop ii industrial/auto-a soic industrial 2.2 3.0 3.6 55 2 2.5 15 20 1 7 a 15 v cc a 13 a 12 a 5 nc we a 7 i/o 4 i/o 5 a 4 i/o 6 i/o 7 v ss a 11 a 10 a 1 v ss i/o 0 a 2 a 8 a 6 a 3 a 0 v cc i/o 1 i/o 2 i/o 3 a 17 a 18 a 16 ce oe a 9 a 14 d e b a c f g h nc 36-ball vfbga pinout top view 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 32-pin soic/tsop ii pinout top view a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v ss v cc a 18 we oe ce notes 2. soic package is available only in 55 ns speed bin. 3. nc pins are not connected on the die. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 4 of 16 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature... ............... ............... ?65 c to +150 c ambient temperature with power applied ............................................. 55 c to +125 c supply voltage to ground potential ........................................?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs in high-z state [5, 6] ......................?0.3 v to v cc(max) + 0.3 v dc input voltage [5, 6] ....................?0.3 v to v cc(max) + 0.3 v output current into outputs (low) .............................. 20 ma static discharge voltage.......................................... > 2001 v (mil-std-883, method 3015) latch up current...................................................... > 200 ma operating range product range ambient temperature v cc [7] cy62148ev30 industrial/ auto-a ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics (over the operating range) parameter description test conditions ?45 (industr ial/auto-a) ?55 [8] unit min typ [9] max min typ [9] max v oh output high voltage i oh = ?0.1 ma 2.0 ? ? 2.0 ? ? v i oh = ?1.0 ma, v cc > 2.70 v 2.4 ? ? 2.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.4 ? ? 0.2 v i ol = 2.1 ma, v cc > 2.70 v ? ? 0.4 ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 v 1.8 ? v cc + 0.3 v v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 v 2.2 ? v cc + 0.3 v v v il input low voltage v cc = 2.2 v to 2.7 v for vfbga and tsop ii package ?0.3 ? 0.6 ? ? ? v for soic package ? ? ? ?0.3 ? 0.4 [10] v v cc = 2.7 v to 3.6 v for vfbga and tsop ii package ?0.3 ? 0.8 ? ? ? v for soic package ? ? ? ?0.3 ? 0.6 [10] i ix input leakage current gnd < v i < v c ?1 ? +1 ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max), i out = 0 ma, cmos levels ? 15 20 ? 15 20 ma f = 1 mhz ? 2 2.5 ? 2 2.5 i sb1 [11] automatic ce power down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v f = f max (address and data only), f = 0 (oe and we ), v cc = 3.60 v ?1 7 ?1 7 ? a i sb2 [11] automatic ce power down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?1 7 ?1 7 ? a notes 5. v il(min) = ?2.0v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 7. full device ac operation assumes a minimum of 100 ? s ramp time from 0 to v cc(min) and 200 ? s wait time after v cc stabilization. 8. soic package is available only in 55 ns speed bin. 9. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 10. under dc conditions the device meets a v il of 0.8v (for v cc range of 2.7 v to 3.6 v) and 0.6 v (for v cc range of 2.2 v to 2.7 v). however, in dynamic conditions input low voltage applied to the device must not be higher than 0.6v and 0.4v for the above ranges. this is applicable to soic package only. refer to an13470 for details. 11. chip enable (ce ) must be high at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating.
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 5 of 16 capacitance parameter [12] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [12] description test conditions vfbga package tsop ii package soic package unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 72 75.13 55 ? c/w ? jc thermal resistance (junction to case) 8.86 8.95 22 ? c/w figure 1. ac test loads and waveforms parameters 2.50 v 3.0 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [13] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [12] data retention current v cc = 1.5 v, ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ind?l/auto-a ? 0.8 7 ? a t cdr [14] chip deselect to data retention time 0??ns t r [15] operation recovery time cy62148ev30ll-45 45 ? ? ns cy62148ev30ll-55 55 ? ? ? figure 2. data retention waveform notes 12. .tested initially and after any design or proce ss changes that may affect these parameters. 13. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 14. tested initially and after any design or process changes that may affect these parameters. 15. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 6 of 16 switching characteristics (over the operating range) parameter [16] description -45 (industrial/auto-a) -55 [17] unit min max min max read cycle t rc read cycle time 45 ? 55 ? ns t aa address to data valid ? 45 ? 55 ns t oha data hold from address change 10 ? 10 ? ns t ace ce low to data valid ? 45 ? 55 ns t doe oe low to data valid ? 22 ? 25 ns t lzoe oe low to low z [18] 5?5?ns t hzoe oe high to high z [18, 19] ?18?20ns t lzce ce low to low z [18] 10?10?ns t hzce ce high to high z [18, 19] ?18?20ns t pu ce low to power up 0 ? 0 ? ns t pd ce high to power up ? 45 ? 55 ns write cycle [20] t wc write cycle time 45 ? 55 ? ns t sce ce low to write end 35 ? 40 ? ns t aw address setup to write end 35 ? 40 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 35 ? 40 ? ns t sd data setup to write end 25 ? 25 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high z [18, 19] ?18?20ns t lzwe we high to low z [18] 10?10?ns notes 16. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ac test loads and waveforms on page 5. 17. soic package is available only in 55 ns speed bin. 18. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 19. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 20. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that terminates th e write.
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 7 of 16 switching waveforms figure 3. read cycle no. 1 (address transition controlled) [21, 22] figure 4. read cycle no. 2 (oe controlled) [22, 23] figure 5. write cycle no. 1 (we controlled, oe high during write) [24, 25] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 26 notes 21. device is continuously selected. oe , ce = v il . 22. we is high for read cycles. 23. address valid before or similar to ce transition low. 24. data i/o is high impedance if oe = v ih . 25. if ce goes high simultaneously with we high, the output remains in high impedance state. 26. during this period, the i/os are in output state. do not apply input signals.
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 8 of 16 figure 6. write cycle no. 2 (ce controlled) [27, 28] figure 7. write cycle no. 3 (we controlled, oe low) [28] truth table ce [30] we oe inputs/outputs mode power h x x high z deselect/power down standby (i sb ) l h l data out read active (i cc ) l h h high z output disabled active (i cc ) l l x data in write active (i cc ) switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 29 notes 27. data i/o is high impedance if oe = v ih . 28. if ce goes high simultaneously with we high, the output remains in high impedance state. 29. during this period, the i/os are in output state. do not apply input signals. 30. chip enable must be at cmos levels (not floating). intermediate voltage levels on this pin is not permitted.
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 9 of 16 ordering information speed (ns) ordering code package diagram package type operating range 45 cy62148ev30ll-45bvi 51-85149 36-ball vfbga industrial cy62148ev30ll-45bvxi 51-85149 36-ball vfbga (pb-free) cy62148ev30ll-45zsxi 51-85095 32-pin tsop ii (pb-free) CY62148EV30LL-45ZSXA 51-85095 32-pin tsop ii (pb-free) automotive-a 55 cy62148ev30ll-55sxi 51-85081 32- pin soic (pb-free) industrial contact your local cypress sales repres entative for availability of these parts. ordering code definitions company id: cy = cypress family code: mobl sram family density = 4-mbit bus width = 8 e = process technology 90 nm voltage range = 3 v typical ll = low power xx = speed grade = 45 ns / 55 ns package type: bv / bvx = vfbga / vfbga (pb -free) zsx = tsop ii (pb-free) sx = soic (pb-free) temperature grade: i = industrial, a = automotive cy -xx xxx 621 4 8 ev30 ll i/a
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 10 of 16 package diagrams figure 8. 36-ball vfbga (6 x 8 x 1 mm), 51-85149 51-85149 *d
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 11 of 16 figure 9. 32-pin tsop ii, 51-85095 package diagrams (continued) 51-85095 *b
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 12 of 16 figure 10. 32-pin (450 mil) molded soic, 51-85081 package diagrams (continued) 51-85081-*c
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 13 of 16 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine ball grid array we write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes pf pico farad c degree celsius wwatts
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 14 of 16 document history page document title: cy62148ev30 mobl ? 4-mbit (512 k 8) static ram document number: 38-05576 rev. ecn submissio n date orig. of change description of change ** 223225 see ecn aju new data sheet *a 247373 see ecn syt changed from advance information to preliminary moved product portfolio to page 2 changed v cc stabilization time in footnote #7 from 100 ? s to 200 ? s changed i ccdr from 2.0 ? a to 2.5 ? a changed typo in data retention characteristics (t r ) from 100 ? s to t rc ns changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bin changed t hzoe , t hzwe from 12 to 15 ns for 35 ns speed bin and 15 to 18 ns for 45 ns speed bin changed t sce from 25 to 30 ns for 35 ns speed bin and 40 to 35 ns for 45 ns speed bin changed t hzce from 12 to 18 ns for 35 ns speed bin and 15 to 22 ns for 45 ns speed bin changed t sd from 15 to 18 ns for 35 ns speed bin and 20 to 22 ns for 45 ns speed bin changed t doe from 15 to 18 ns for 35 ns speed bin changed ordering information to include pb-free packages *b 414807 see ecn zsd changed from preliminary information to final changed the address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? removed 35ns speed bin removed ?l? versio n of cy62148ev30 changed ball c3 from dnu to nc. removed the redundant footnote on dnu. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max changed i sb1 and i sb2 typ values from 0.7 ? a to 1 ? a and max values from 2.5 ? a to 7 ? a. changed the ac test load capacitance value from 50pf to 30pf. changed i ccdr from 2.5 ? a to 7 ? a. added i ccdr typical value. changed t lzoe from 3 ns to 5 ns changed t lzce and t lzwe from 6 ns to 10 ns changed t hzce from 22 ns to 18 ns changed t pwe from 30 ns to 35 ns. changed t sd from 22 ns to 25 ns. updated the package diagram 36-pin vfbga from *b to *c added 32-pin soic package diagram and pin diagram updated the ordering information table and replaced the package name column with package diagram. *c 464503 see ecn nxr included automotive range in product offering updated thermal resistance table updated the ordering information *d 833080 see ecn vkn added footnote 8 added v il spec for soic package *e 890962 see ecn vkn removed automotive part and its related information added footnote 2 related to soic package added footnote 9 related to i sb2 added ac values for 55 ns industrial-soic range updated ordering information table
cy62148ev30 mobl ? document #: 38-05576 rev. *l page 15 of 16 *f 987940 see ecn vkn changed v ol spec from 0.4v to 0.2v for soic package at i ol = 0.1 ma changed v il spec from 0.6v to 0.4v for soic package at v cc = 2.2v to 2.7v updated footnote 8 made footnote 9 applicable for both i sb2 and i ccdr *g 2548575 08/05/08 nxr added auto-a information. included -45bvi *h 2769239 09/25/09 vkn/ aesa included -45bvi in the ordering information table *i 2944332 06/04/2010 vkn added footnote related to chip enable in truth table updated package diagrams *j 3007403 08/13/2010 aju updated new template. *k 3110202 12/14/2010 pras updated logic block diagram and ordering code definitions. *l 3302901 07/06/2011 rame updated all the notes. updated package diagram 51-85095. updated ordering code definitions. removed the references of an1094. updated as per template. document title: cy62148ev30 mobl ? 4-mbit (512 k 8) static ram document number: 38-05576 rev. ecn submissio n date orig. of change description of change
document #: 38-05576 rev. *l revised july 6, 2011 page 16 of 16 mobl is a registered trademark, and more battery life is a tradem ark, of cypress semiconductor. all product and company names m entioned in this document are the trademarks of their respective holders. all products and company nam es mentioned in this document may be the trademarks of thei r respective holders. cy62148ev30 mobl ? ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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